Two papers from our lab have been accepted for publication in TCAS-I.
🎊 “A Low-OSR 5th-Order Noise Shaping SAR ADC in a Two-Amplifier EF-EF-CIFF Structure with PVT-Robust V-T-V Converters”
Congratulations to 寶樹!
🎊 “A 128 × 128 Dual-Resolution CMOS Image Sensor With In-Sensor Temporal and Spatial Gradient Calculations for Optical Flow Pre-Processing”
Congratulations to 亮瑜!
閱讀全文We are pleased to announce that several papers from our lab have been accepted by two international conferences, “IEEE A-SSCC 2026”and“IEEE Sensors 2026”.
✨ “An Intelligent Vision Sensor with In-Pixel Timestamp Encoding for EMD-Inspired Motion Estimation”
Congratulations to 柏安!
✨ “A 9.3-Bit 1.23-GS/s Time-Interleaved Hybrid ADC with Shared Fine Stage Using Gm-Switching VTC”
Congratulations to 永駿!
✨ “A Motion-Adaptive Edge-Extraction Image Sensor with Dynamic Detection and Static Edge Persistence”
Congratulations to 思璇!
✨ “A 128×128 CMOS Image Sensor with In-Pixel Temporal-Occupancy Extraction for Single-Frame Blur-Based Fast Motion Estimation”
Congratulations to 婷婕!
✨ “A 0.8V 135fps 8T2C PWM Frame-Difference Vision Sensor with Ramp-Domain Background Calibration for Multimode Vision Sensing”
Congratulations to 郁翔!
Congratulations to all the authors on their outstanding work and achievements!
閱讀全文We are pleased to announce that four papers from our lab have been accepted for presentation and publication at The 37th VLSI Design/CAD Symposium.
🏆 “A Two-Channel Time-Interleaved 1.28-GS/s 8.6-bit Hybrid SAR/TDC ADC With a Dual-Mode Comparator and PWM-Based VTC”
Congratulations to 昱翔 on receiving the Best Paper Award!
🎊 “A Frame-Differencing CMOS Image Sensor for >120-dB Temporal Event Detection Dynamic Range Using Pixel-Grouped Multiple Exposure”
Congratulations to John!
🎊 “A 0.8-V 8T2C PWM Frame-Difference Vision Sensor with Ramp-Domain Background Calibration for Multimode Processing-in-Sensor Applications”
Congratulations to 郁翔!
🎊 “A Motion-Adaptive Edge-Extraction Image Sensor with Dynamic Detection and Static Edge Persistence”
Congratulations to 思璇!
Congratulations to all the authors on their excellent work and achievements!
閱讀全文We are pleased to announce that two theses from our lab have been recognized in the 「TICD 第23屆（115年度）博碩士論文獎」
🏆「一個應用於高線性度與低雜訊微測輻射儀影像之列平行讀出晶片，具備重建式電流模讀出與部分直流抵銷技術」
Congratulations to 家緯!
🏆「一個內建時間記憶像素並支援即時光流估測之 126×126 仿生基本運動檢測器架構視覺感測器」
Congratulations to 柏安!
Congratulations to both award recipients on this outstanding achievement!
閱讀全文「一個9.3位元每秒取樣十二點三億次之時間交錯混合式類比數位轉換器採用細級共享與跨導切換式電壓時間轉換器」
Congrats to 永駿、昱翔!!!
“A Frame-Differencing CMOS Image Sensor for >120-dB HDR Temporal Event Detection Using Pixel-Grouped Multiple Exposure” Accepted for presentation and publication
Congrats to John!!!
閱讀全文Congrats to our members!
All articles are available on IEEEXplore.
[1] Chih-Cheng Chen, Chih-Cheng Hsieh, “A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter,” to be presented in 2021 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2021.
閱讀全文Congrats to our members!
All articles are available on IEEEXplore.
[1] You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, Chih-Cheng Hsieh, “A Monolithic Optical Encoder Using CMOS Image Sensor with Background Light Cancellation,” to be presented in 2020 IEEE International Symp. on Circuits and Systems (ISCAS), Oct. 2020.
閱讀全文Congrats to our members!
All articles are available on IEEEXplore.
[1] Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[2] J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, S-S. Sheu, S-H. Li, H-Y. Lee, S-C. Chang, S. Yu, M-F. Chang, “A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[3] C-X. Xue, T-Y. Huang, J-S. Liu, T-W. Chang, H-Y. Kao, J-H. Wang, T-W. Liu, S-Y. Wei, S-P. Huang, W-C. Wei, Y-R. Chen, T-H. Hsu, Y-K. Chen, Y-C. Lo, T-H. Wen, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[4] X. Si1, Y-N. Tu, W-H. Huang, J-W. Su, P-J. Lu, J-H. Wang, T-W. Liu, S-Y. Wu, R. Liu, Y-C. Chou, Z. Zhang, S-H. Sie, W-C. Wei, Y-C. Lo, T-H. Wen, T-H. Hsu, Y-K. Chen, W. Shih, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, N-C. Lien, W-C. Shih, Y. He, Q. Li, M-F. Chang, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[1] [Invited] Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh, “AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device,” 2019 IEEE International Electron Devices Meeting (IEDM), Dec. 2019.
閱讀全文Congrats to our members!
All articles are available on IEEEXplore.
[1] Kwuang-Han Chang and Chih-Cheng Hsieh, “A Calibration-Free 13-bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” accepted by IEEE Journal of Solid-State Circuits.
[1] Tzu-Hsiang Hsu, R.-S. Liu, C.-C. Lo, K.-T. Tang, M.-F. Chang, and Chih-Cheng Hsieh, “A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction,” accepted by 2019 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2019.
[1] K.-T. Tang, W.-C. Wei, Z.-W. Yeh, T.-H. Hsu, Y.-C. Chiu, C.-X. Xue, Y.-C. Kuo, T.-H. Wen, M.-S. Ho, C.-C. Lo, R.-S. Liu, Chih-Cheng Hsieh and M.-F. Chang, “Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices,” 2019 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2019.
[1] Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
[2] You-Shin Chen, T.-H. Hsu, C.-W. Chen, Chih-Cheng Hsieh, “A Low Noise Optical Encoder with Background Light Cancellation Using Photodiodes in Series,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
[3] Yi-Hsuan Lin, Chih-Cheng Hsieh, “An Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
閱讀全文Congrats to our members!
All articles are available on IEEEXplore.
[1] Kwuang-Han Chang and Chih-Cheng Hsieh, ” A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors,” accepted by IEEE Journal of Solid-State Circuits.
[2] Sung-En Hsieh, and Chih-Cheng Hsieh, “A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator,” accepted by IEEE Journal of Solid-State Circuits.
[1] Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh, “A 40MS/S 12-Bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting,” to be published in 2019 IEEE International Symp. on Circuits and Systems (ISCAS), May. 2019.
[1] C-X. Xue, W-H. Chen, J-S. Liu, J-F. Li, W-Y. Lin, W-E. Lin, J-H. Wang, W-C. Wei, T-W. Chang, T-C. Chang, T-Y. Huang, H-Y. Kao, S-Y. Wei, Y-C. Chiu, C-Y. Lee, C-C. Lo, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN-Based AI Edge Processors,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[2] X. Si1, J-J. Chen1, Y-N. Tu1, W-H. Huang, J-H. Wang, W-C. Wei, S-Y. Wu, X. Sun, R. Liu, S. Yu, R-S. Liu1, Chih-Cheng Hsieh, K-T. Tang, Q. Li, M-F. Chang, “Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN- Based Machine Learning,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[1] Kwuang-Han Chang, and Chih-Cheng Hsieh, “A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.
[2] Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, and Chih-Cheng Hsieh, “A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.
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