Congrats to our members!
All articles are available on IEEEXplore.
[1] Chih-Cheng Chen, Chih-Cheng Hsieh, “A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter,” to be presented in 2021 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2021.
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All articles are available on IEEEXplore.
[1] You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, Chih-Cheng Hsieh, “A Monolithic Optical Encoder Using CMOS Image Sensor with Background Light Cancellation,” to be presented in 2020 IEEE International Symp. on Circuits and Systems (ISCAS), Oct. 2020.
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All articles are available on IEEEXplore.
[1] Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[2] J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, S-S. Sheu, S-H. Li, H-Y. Lee, S-C. Chang, S. Yu, M-F. Chang, “A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[3] C-X. Xue, T-Y. Huang, J-S. Liu, T-W. Chang, H-Y. Kao, J-H. Wang, T-W. Liu, S-Y. Wei, S-P. Huang, W-C. Wei, Y-R. Chen, T-H. Hsu, Y-K. Chen, Y-C. Lo, T-H. Wen, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[4] X. Si1, Y-N. Tu, W-H. Huang, J-W. Su, P-J. Lu, J-H. Wang, T-W. Liu, S-Y. Wu, R. Liu, Y-C. Chou, Z. Zhang, S-H. Sie, W-C. Wei, Y-C. Lo, T-H. Wen, T-H. Hsu, Y-K. Chen, W. Shih, C-C. Lo, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, N-C. Lien, W-C. Shih, Y. He, Q. Li, M-F. Chang, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
[1] [Invited] Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Meng-Fan Chang, and Chih-Cheng Hsieh, “AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device,” 2019 IEEE International Electron Devices Meeting (IEDM), Dec. 2019.
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All articles are available on IEEEXplore.
[1] Kwuang-Han Chang and Chih-Cheng Hsieh, “A Calibration-Free 13-bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” accepted by IEEE Journal of Solid-State Circuits.
[1] Tzu-Hsiang Hsu, R.-S. Liu, C.-C. Lo, K.-T. Tang, M.-F. Chang, and Chih-Cheng Hsieh, “A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction,” accepted by 2019 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2019.
[1] K.-T. Tang, W.-C. Wei, Z.-W. Yeh, T.-H. Hsu, Y.-C. Chiu, C.-X. Xue, Y.-C. Kuo, T.-H. Wen, M.-S. Ho, C.-C. Lo, R.-S. Liu, Chih-Cheng Hsieh and M.-F. Chang, “Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices,” 2019 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2019.
[1] Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
[2] You-Shin Chen, T.-H. Hsu, C.-W. Chen, Chih-Cheng Hsieh, “A Low Noise Optical Encoder with Background Light Cancellation Using Photodiodes in Series,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
[3] Yi-Hsuan Lin, Chih-Cheng Hsieh, “An Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
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All articles are available on IEEEXplore.
[1] Kwuang-Han Chang and Chih-Cheng Hsieh, ” A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors,” accepted by IEEE Journal of Solid-State Circuits.
[2] Sung-En Hsieh, and Chih-Cheng Hsieh, “A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator,” accepted by IEEE Journal of Solid-State Circuits.
[1] Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh, “A 40MS/S 12-Bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting,” to be published in 2019 IEEE International Symp. on Circuits and Systems (ISCAS), May. 2019.
[1] C-X. Xue, W-H. Chen, J-S. Liu, J-F. Li, W-Y. Lin, W-E. Lin, J-H. Wang, W-C. Wei, T-W. Chang, T-C. Chang, T-Y. Huang, H-Y. Kao, S-Y. Wei, Y-C. Chiu, C-Y. Lee, C-C. Lo, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN-Based AI Edge Processors,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[2] X. Si1, J-J. Chen1, Y-N. Tu1, W-H. Huang, J-H. Wang, W-C. Wei, S-Y. Wu, X. Sun, R. Liu, S. Yu, R-S. Liu1, Chih-Cheng Hsieh, K-T. Tang, Q. Li, M-F. Chang, “Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN- Based Machine Learning,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[1] Kwuang-Han Chang, and Chih-Cheng Hsieh, “A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.
[2] Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, and Chih-Cheng Hsieh, “A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.
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All articles are available on IEEEXplore.
[1] Albert Yen-Chih Chiou, and Chih-Cheng Hsieh, “An ULV PWM CMOS Imager with Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting,” accepted by IEEE Journal of Solid-State Circuits.
[2] Sung-En Hsieh, Chen-Che Kao, and Chih-Cheng Hsieh, “A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator with Noise Optimization,” IEEE Journal of Solid-State Circuits, vol 53, no. 10, pp. 2763-2771, Oct. 2018.
[3] Tzu-Hsiang Hsu, Ting Liao, Nien-An Lee, and Chih-Cheng Hsieh, “A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique,” IEEE Journal of Solid-State Circuits, vol 53, no. 10, pp. 2898-2905, Oct. 2018.
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Congrats to our members!
All articles are available on IEEEXplore.
[1] Sung-En Hsieh, Chen-Che Kao, and Chih-Cheng Hsieh, ” A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator with Noise Optimization,” Accepted by IEEE Journal of Solid-State Circuits.
[2] Tzu-Hsiang Hsu, Ting Liao, Nien-An Lee, and Chih-Cheng Hsieh, ” A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique,” Accepted by IEEE Journal of Solid-State Circuits.
[3] Sung-En Hsieh and Chih-Cheng Hsieh, ” A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC,” IEEE Journal of Solid-State Circuits, vol 53, no. 9, pp. 2595-2603, Sept. 2018.
[4] Kwuang-Han Chang and Chih-Cheng Hsieh, “A 12-bit 150-MS/s Sub-Radix-3 SAR ADC with Switching Miller Capacitance Reduction,” IEEE Journal of Solid-State Circuits, vol 53, no. 6, pp. 1755-1764, June. 2018.
[1] H Chen, Y-C Chang, S-R Yeh, Chih-Cheng Hsieh, K-T Tang, P-H Hsieh, Y-T Liao, R Perumel, J-F Chuang, C-C Chang, Y-C Chen, S. H. Chen, S-E Hsieh, Y-P Chen, Y-T Chen, T-H Liu, Y-M Chang, W-C Lai, C-Y Wu, Y-H Chen, Y-C Weng, “Development of a Multisite, Closed-loop Neuromodulator for the Theranosis of Neural Degenerative Diseases,” in 2018 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2018.
[1] Sung-En Hsieh and Chih-Cheng Hsieh, “A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator,” International Solid-State Circuits Conference (ISSCC), Feb. 2018.
[2] W-H. Chen, K-X. Li, W-Y. Lin, K-H. Hsu, P-Y. Li, C-H. Yang, C-X. Xue, E-Y. Yang, Y-K. Chen, Y-S. Chang, T-H. Hsu, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors,” International Solid-State Circuits Conference (ISSCC), Feb. 2018.
[1] Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A 64×64 Pixels CMOS Image Sensor Using Pseudo Multiple Sampling with Column CDS,” in 2018 VLSI Design/CAD Symposium, Tainan, Taiwan, Aug. 7-10, 2018.
[2] Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interferer Rejection,” in 2018 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 7-10, 2018.
[3] Min-Rui Wu, Sung-En Hsieh, Chih-Cheng Hsieh, “A 12-bit SAR ADC with split switching DAC,” in 2018 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 7-10, 2018.
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Congrats to our members Sung-En Hsieh and Chih-Cheng Hsieh, a new paper “A 0.4V 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator” being accepted by 2018 IEEE International Solid-State Circuits Conference (ISSCC).
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