Congrats to our members!

All articles are available on IEEEXplore.

IEEE Journal of Solid-State Circuits (JSSC)

[1]            Kwuang-Han Chang and Chih-Cheng Hsieh, ” A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors,” accepted by IEEE Journal of Solid-State Circuits.

[2]            Sung-En Hsieh, and Chih-Cheng Hsieh, “A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator,” accepted by IEEE Journal of Solid-State Circuits.

IEEE International Symp. on Circuits and Systems (ISCAS)

[1]            Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh, “A 40MS/S 12-Bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting,” to be published in 2019 IEEE International Symp. on Circuits and Systems (ISCAS), May. 2019.

International Solid-State Circuits Conference (ISSCC)

[1]            C-X. Xue, W-H. Chen, J-S. Liu, J-F. Li, W-Y. Lin, W-E. Lin, J-H. Wang, W-C. Wei, T-W. Chang, T-C. Chang, T-Y. Huang, H-Y. Kao, S-Y. Wei, Y-C. Chiu, C-Y. Lee, C-C. Lo, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN-Based AI Edge Processors,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.

[2]            X. Si1, J-J. Chen1, Y-N. Tu1, W-H. Huang, J-H. Wang, W-C. Wei, S-Y. Wu, X. Sun, R. Liu, S. Yu, R-S. Liu1, Chih-Cheng Hsieh, K-T. Tang, Q. Li, M-F. Chang, “Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN- Based Machine Learning,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.

IEEE Asian Solid-State Circuits Conference (ASSCC)

[1]            Kwuang-Han Chang, and Chih-Cheng Hsieh, “A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.

[2]            Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, and Chih-Cheng Hsieh, “A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.

Congrats to our members!

All articles are available on IEEEXplore.

IEEE Journal of Solid-State Circuits (JSSC)

[1]            Sung-En Hsieh, Chen-Che Kao, and Chih-Cheng Hsieh, ” A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator with Noise Optimization,” Accepted by IEEE Journal of Solid-State Circuits.

[2]            Tzu-Hsiang Hsu, Ting Liao, Nien-An Lee, and Chih-Cheng Hsieh, ” A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique,” Accepted by IEEE Journal of Solid-State Circuits.

[3]            Sung-En Hsieh and Chih-Cheng Hsieh, ” A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC,” IEEE Journal of Solid-State Circuits, vol 53, no. 9, pp. 2595-2603, Sept. 2018.

[4]            Kwuang-Han Chang and Chih-Cheng Hsieh, “A 12-bit 150-MS/s Sub-Radix-3 SAR ADC with Switching Miller Capacitance Reduction,” IEEE Journal of Solid-State Circuits, vol 53, no. 6, pp. 1755-1764, June. 2018.

2018 IEEE Symposia on VLSI Circuits

[1]            H Chen, Y-C Chang, S-R Yeh, Chih-Cheng Hsieh, K-T Tang, P-H Hsieh, Y-T Liao, R Perumel, J-F Chuang, C-C Chang, Y-C Chen, S. H. Chen, S-E Hsieh, Y-P Chen, Y-T Chen, T-H Liu, Y-M Chang, W-C Lai, C-Y Wu, Y-H Chen, Y-C Weng, “Development of a Multisite, Closed-loop Neuromodulator for the Theranosis of Neural Degenerative Diseases,” in 2018 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2018.

2018 International Solid-State Circuits Conference (ISSCC)

[1]            Sung-En Hsieh and Chih-Cheng Hsieh, “A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator,” International Solid-State Circuits Conference (ISSCC), Feb. 2018.

[2]            W-H. Chen, K-X. Li, W-Y. Lin, K-H. Hsu, P-Y. Li, C-H. Yang, C-X. Xue, E-Y. Yang, Y-K. Chen, Y-S. Chang, T-H. Hsu, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors,” International Solid-State Circuits Conference (ISSCC), Feb. 2018.

2018 VLSI Design/CAD Symposium

[1]            Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A 64×64 Pixels CMOS Image Sensor Using Pseudo Multiple Sampling with Column CDS,” in 2018 VLSI Design/CAD Symposium, Tainan, Taiwan, Aug. 7-10, 2018.

[2]            Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interferer Rejection,” in 2018 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 7-10, 2018.

[3]            Min-Rui Wu, Sung-En Hsieh, Chih-Cheng Hsieh, “A 12-bit SAR ADC with split switching DAC,” in 2018 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 7-10, 2018.