Congrats to our members!
All articles are available on IEEEXplore.
[1] You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, Chih-Cheng Hsieh, “A Monolithic Optical Encoder Using CMOS Image Sensor with Background Light Cancellation,” to be presented in 2020 IEEE International Symp. on Circuits and Systems (ISCAS), Oct. 2020.
Congrats to our members!
All articles are available on IEEEXplore.
[1] Kwuang-Han Chang and Chih-Cheng Hsieh, “A Calibration-Free 13-bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” accepted by IEEE Journal of Solid-State Circuits.
[1] Tzu-Hsiang Hsu, R.-S. Liu, C.-C. Lo, K.-T. Tang, M.-F. Chang, and Chih-Cheng Hsieh, “A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction,” accepted by 2019 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2019.
[1] K.-T. Tang, W.-C. Wei, Z.-W. Yeh, T.-H. Hsu, Y.-C. Chiu, C.-X. Xue, Y.-C. Kuo, T.-H. Wen, M.-S. Ho, C.-C. Lo, R.-S. Liu, Chih-Cheng Hsieh and M.-F. Chang, “Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices,” 2019 IEEE Symposia on VLSI Circuits (VLSI Symposia), Jun. 2019.
[1] Tzu-Hsiang Hsu, Chih-Cheng Hsieh, “A 0.5V Real-time Computational CMOS Image Sensor with Programmable Kernel for Always-on Feature Extraction,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
[2] You-Shin Chen, T.-H. Hsu, C.-W. Chen, Chih-Cheng Hsieh, “A Low Noise Optical Encoder with Background Light Cancellation Using Photodiodes in Series,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
[3] Yi-Hsuan Lin, Chih-Cheng Hsieh, “An Energy-Efficient 12b 20MS/s Time-Interleaved SAR ADC,” in 2019 VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 6-9, 2019.
Congrats to our members!
All articles are available on IEEEXplore.
[1] Kwuang-Han Chang and Chih-Cheng Hsieh, ” A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors,” accepted by IEEE Journal of Solid-State Circuits.
[2] Sung-En Hsieh, and Chih-Cheng Hsieh, “A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator,” accepted by IEEE Journal of Solid-State Circuits.
[1] Yung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh, “A 40MS/S 12-Bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting,” to be published in 2019 IEEE International Symp. on Circuits and Systems (ISCAS), May. 2019.
[1] C-X. Xue, W-H. Chen, J-S. Liu, J-F. Li, W-Y. Lin, W-E. Lin, J-H. Wang, W-C. Wei, T-W. Chang, T-C. Chang, T-Y. Huang, H-Y. Kao, S-Y. Wei, Y-C. Chiu, C-Y. Lee, C-C. Lo, Y-C. King, C-J. Lin, R-S. Liu, Chih-Cheng Hsieh, K-T. Tang, M-F. Chang, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN-Based AI Edge Processors,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[2] X. Si1, J-J. Chen1, Y-N. Tu1, W-H. Huang, J-H. Wang, W-C. Wei, S-Y. Wu, X. Sun, R. Liu, S. Yu, R-S. Liu1, Chih-Cheng Hsieh, K-T. Tang, Q. Li, M-F. Chang, “Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN- Based Machine Learning,” International Solid-State Circuits Conference (ISSCC), Feb. 2019.
[1] Kwuang-Han Chang, and Chih-Cheng Hsieh, “A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.
[2] Hsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, and Chih-Cheng Hsieh, “A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections,” in Proc. of 2018 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018.